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January 28, 2001: Preliminary design concept laid out
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The various modules have been designed in terms of functionality and input/output characteristics. The modules are the random number generator module (RNG), the selection module (SM), the crossover module (XM), the mutation module (MM), the fitness module (FM), the input instantiation module (IIM), and the control unit (CU).
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The system operation has also been defined and analyzed. The memory architecture is being investigated into, as well as the memory interface to the external world, including software.
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February 20, 2001: JBits investigation is underway
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JBits is needed for various goals, including the configuration and the readback of the FPGA; the provision of test case inputs and experimental outputs; the partial reconfiguration characteristic of Virtex FPGAs; and the construction of the real-time bitstream.
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As long as the designs are kept synchronous, then JBits will perform the intended functionalities mentioned above. To keep all designs synchronous, two basic rules have to be adhered to: 1) Guarantee that the clocks are not gated and 2) Guarantee the lack of asynchronous feedback paths. The first rule is quite simple to follow, as it involves the explicit watchful eye of an intermediate VHDL designer, but the second rule is broken up into two smaller sub-rules. The first sub-rule is to make sure that all clocks are driven by the global clock, and the second sub-rule is to make sure that all look-up table (LUT) inputs are only driven by the outputs of flip-flops. Upon the observance of these rules, JBits can be used to instantiate digital circuits for real-time testing and fitness evaluation.
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March 26, 2001: Exceeded logic constraints on H.O.T. II platform
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During the synthesis phase, the logic requirements of the project have exceeded the physical constraints provided to us by the H.O.T. II prototyping platform. The current results do not include the FM and the IIM, and are as follows: 820/784 CLBs and 968/1400 FFs. The excess in logic will be even greater once the remaining modules are implemented and consequently synthesized.
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We have requested and have been approved for a Xilinx University Donation through the XUP. The donation involves equipping us with the two FPGAs that reside on the H.O.T. II platform, and thus through this donation, we have secured enough funds to upgrade to the H.O.T. II - XL platform, which is the extended version of the product. This will allow us to include the remaining modules and still have ample logic resources for further re-spins and/or features.
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April 19, 2001: Datapath/controlpath development complete
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ASM design for all responsible modules has been completed. Hardware implementation and functional simulation have also been successfully completed. All modules were designed and implemented using ASM datapath and controlpath methodologies, thus simplifying the future debugging process in order to systematically eliminate faults by the exact realization of what module is in which state.
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Numerous testbenches were written in order to simulate the VHDL code for the different modules. A main testbench was also designed and implemented, which effectively simulates the software response to the various assertions (and de-assertions) of status signals in hardware. The software "sees" into the hardware through various control registers, mainly one for each module.
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May 15, 2001: Presentation of research at CCECE in Toronto, Canada
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The research was presented as paper #227 at the Canadian Conference on Electrical and Computer Engineering 2001 (CCECE 2001). It was presented in the Intelligent Systems II session on Tuesday, May 15th, 2001. The session was jointly chaired by Dr. Bruno Di-Stefano and Dr. Kostas Plataniotis.
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The title of the paper was "Circuit synthesis evolution using a hardware-based genetic algorithm". A copy of the paper can be found below.
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The title of the presentation was "GaS: Genetic Algorithm Synthesis - Technology Mapping Evolved". A copy of the presentation can be found below.
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June 14, 2001: Splash and input parameters screens of GUI are complete
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The initial screens of the graphical user interface (GUI) have been developed in Java, under the JDK 1.3.1 from Sun Microsystems. The development is being undertaken in Visual Age for Java, provided by IBM as a software donation to the University of Ottawa.
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The input parameters screens consist of user-friendly formatted text boxes, check boxes and various other input objects. Altogether, they ease the user interaction and mask the detailed interworkings of the complete system.
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In this research, we propose a scheme based on a hardware
implementation of a genetic
algorithm,
to evolve the minimized
logic solution of a defined input function. The minimization
will be one of resource usage, more precisely of
look-up tables (LUTs). The design aids
in the difficult issue
of technology mapping, as well as multi-level logic synthesis.
The approach undertaken in this research involves
intrinsic hardware evolution, where the
circuit solution is
evolved online, and the output is a minimized structure
of the circuit. Our architecture is outlined and briefly discussed,
while our current results
are presented and analyzed.
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