Feasible Tests

The Sr wrt requirement r1 (corresponding to TUT = T3) for the ATM System is obtained from the STSG program as follows:
In the above figure all generated tests are infeasible. A feasible test for requirement r1 should be: T1 T2 T2 T2 T3

Note that this feasible test also exhibits the same SIP as the last one in the figure.
The issue of forming feasible tests remains to be tackled in the current STSG program. A possible solution is outlined in Olfa's thesis.