The specification of a system in diverse areas such as lexical analysis, pattern matching, telephone systems, machine learning, and communications protocols can be modeled by a Finite State Machine (FSM).

The fault detection experiment determines, under certain assumptions, whether a given black box implementation of an FSM is functioning correctly with respect to its specification. The experiment consists of applying an input sequence, observing the actual output sequence produced in response to the input sequence, and comparing the actual output sequence to the expected output sequence.

The applied input sequence and the expected output sequence form a test sequence that can be generated by a software tool, called FSM-based Test Sequence Generator whose latest version is TSG version 3.0.

TSG has been developed under the supervision of Professor Hasan Ural of the Telecommumnications Software Engineering Reasearch Group (TSERG), Department of Computer Science, Universitty of Ottawa.