library ieee;
use IEEE.std_logic_1164.all;

package light_states is
		constant HGFR:	std_logic_vector(0 to 1) := "11";
		constant HYFR:	std_logic_vector(0 to 1) := "10";
		constant HRFG:	std_logic_vector(0 to 1) := "01";
		constant HRFY:	std_logic_vector(0 to 1) := "00";
end light_states;

library ieee;
use ieee.std_logic_1164.all;
use work.light_states.all;

entity traffic_light is
port (	c,reset,clk: in std_logic;
		current_state: buffer std_logic_vector(0 to 1));
end traffic_light;

architecture behaviour of traffic_light is

signal 	TS,TL: std_logic := '1';
signal	TL_ST,TS_ST: std_logic :='0';
signal	next_state: std_logic_vector(0 to 1) := HGFR;


begin
	state_machine: process(c,TL,TS)
	begin
		case current_state is
		
		when HGFR =>
					if ( c='1' and TL='0') then
						next_state <= HYFR;
					else
						next_state <= HGFR;
					end if;

		when HYFR =>
					if ( TS='0') then
						next_state <= HRFG;
					else
						next_state <= HYFR;
					end if;

		when HRFG =>
					if ( c='0' or TL='0') then
						next_state <= HRFY;
					else
						next_state <= HRFG;
					end if;

		when HRFY =>
					if ( TS='0') then
						next_state <= HGFR;
					else
						next_state <= HRFY;
					end if;

		when others => null;

	end case;

	end process state_machine;

	memory : process(clk)

		begin
		wait until (clk'event and clk = '1');
			if (reset = '1') then
				current_state <= HGFR;
				TL_ST <= '1';
				TS_ST <= '0';
			else 	current_state <= next_state; 
			end if;
	end process memory;

activateCounter: process(TL_ST,TS_ST)
begin
     	if ( TL_ST= '1' ) then
			TL <= '0' after 400 ns;
		else
    		TL <= '1'; 
     	end if;
    	
		if ( TS_ST = '1' ) then
    	   	TS <= '0' after 200 ns;
		else
			TS <= '1'; 
	   	end if;
end process activateCounter;

end behaviour;