library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

package light_states is
		constant HGFR:	std_logic_vector(0 to 1) := "11";
		constant HYFR:	std_logic_vector(0 to 1) := "10";
		constant HRFG:	std_logic_vector(0 to 1) := "01";
		constant HRFY:	std_logic_vector(0 to 1) := "00";
end light_states;

library ieee;
use IEEE.std_logic_1164.all;
use work.light_states.all;

entity tlc is
port (	c,reset,clk: in std_logic;
		current_state: buffer std_logic_vector(0 to 1));
end tlc;

architecture behaviour of tlc is

signal 	TS,TL: std_logic; 
signal	ST: std_logic := '1';
signal	next_state: std_logic_vector(0 to 1) := HGFR;


begin
	state_machine: process(current_state)
	begin
		case current_state is
		
		when HGFR =>
					if ( c='1' and TL='0') then
						next_state <= HYFR;
					else
						next_state <= HGFR;
					end if;

		when HYFR =>
					if ( TS='0') then
						next_state <= HRFG;
					else
						next_state <= HYFR;
					end if;

		when HRFG =>
					if ( c='0' or TL='0') then
						next_state <= HRFY;
					else
						next_state <= HRFG;
					end if;

		when HRFY =>
					if ( TS='0') then
						next_state <= HGFR;
					else
						next_state <= HRFY;
					end if;

		when others => null;

	end case;

	end process state_machine;

	memory : process(clk)

		begin
			wait until (clk'event and clk = '1');
			if reset = '1' then
				current_state <= HGFR;
				ST <= '1';
			elsif	(current_state = next_state) then
						current_state <= next_state;
						ST <= '0';
				else 	current_state <= next_state; 
						ST <= '1';
				end if;
	end process memory;

	timer : process(ST)

	begin
		if ST = '1' then
			TS <= '1'; TL <= '1';
			TS <= '0' after 5 ns;
			TL <= '0' after 10 ns;
		end if;

	end process timer;

end behaviour;