library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity slight1 is
	port (C,CLK: in bit;
    	  HLB0, HLB1, FLB0, FLB1: out bit);
end slight1;

architecture stateMachine of slight1 is

	constant HighWayGN : std_logic_vector(1 downto 0) := "11"; 
	constant HighWayYW : std_logic_vector(1 downto 0) := "10"; 
	constant FarmWayGN : std_logic_vector(1 downto 0) := "01"; 
	constant FarmWayYW : std_logic_vector(1 downto 0) := "00"; 
	signal TL, TS, TL_ST, TS_ST: std_logic :='0';
	signal currentState: std_logic_vector(1 downto 0) := "11";  
	signal nextState: std_logic_vector(1 downto 0) := "11"; 


begin

  setTimer: process(C)
	begin
		if ((currentState=HighWayGN and C='1') or
			(currentState=FarmWayGN and C='0')) then
			TL_ST <= '1';
			TS_ST <='0';
		end if;
		if ((currentState=HighWayYW) or (currentState=FarmWayYW )) then
    		TS_ST <= '1';
			TL_ST <='0';
		end if;
  end process setTimer;

activateCounter: process(CLK)
begin
	if (CLK'event and CLK='1') then
     	if (TL_ST='1') then
        	TL <= '1' after 200 ns;	
		else
	      	TL <= '0'; 
     	end if;
	end if;
	if (CLK'event and CLK='1') then
     	if (TS_ST = '1') then
        	TS <= '1' after 100 ns;
		else
			TS <= '0'; 
     	end if;
	end if;
end process activateCounter;

 stateChange: process(CLK)
 begin
 	if (CLK'event and CLK='1') then
      	currentState <= nextState;
 	end if;
 end process stateChange;

stateCombination: process (C, TL, TS)
begin

	if (currentState = HighWayGN) then
			HLB0 <= '0';
			HLB1 <= '0';
			FLB0 <= '1';
			FLB1 <= '0';
           if (C='1' and TL='1') then
             nextState <= HighWayYW;
           else
             nextState <= HighWayGN;
           end if;

	elsif (currentState = FarmWayGN) then
            HLB0 <= '1';
			HLB1 <= '0';
			FLB0 <= '0';
		    FLB1 <= '0';
           if (C='1' and TL='1') or (C='0') then
             nextState <= FarmWayYW;
           else
             nextState <= FarmWayGN;
           end if;

	elsif (currentState = HighWayYW) then 
            HLB0 <= '0';
			HLB1 <= '1';
			FLB0 <= '1';
			FLB1 <= '0';
        if (TS='1') then
           nextState <= FarmWayGN;
        else
           nextState <= HighWayYW;
        end if;

	elsif (currentState = FarmWayYW) then 
           
            HLB0 <= '1';
			HLB1 <= '0';
			FLB0 <= '0';
			FLB1 <= '1';
        if (TS='1') then
           nextState <= HighWayGN;
        else
           nextState <= FarmWayYW;
        end if;
     end if;
   end process stateCombination;
end stateMachine;