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Alphabetical List of Reconfigurable Computing Architectures
Last updated: September 14th, 2005

You have ventured onto this page either because you are directly involved in reconfigurable computing research and development or you are interested in reconfigurable architectures in general. Either way, welcome and I hope that the information presented below will be of some value to you. I would like to first thank two people who, through their own original innovations, have greatly influenced the origins of this page: Dr. Steve Guccione from Xilinx and Prof. Dr.-Ing. Reiner Hartenstein from the University of Kaiserslautern. Dr. Guccione has compiled a similar list for FPGA-based Computing Machines, which can be found here. Dr. Hartenstein has written an embedded tutorial covering a decade of reconfigurable computing, which can be found here (paper 111). Its reference, used extensively in the information presented below, is as follows:
Reiner Hartenstein: A Decade of Reconfigurable Computing: a Visionary Retrospective; DATE 2001, Int'l Conference on Design Automation and Testing in Europe - and Exhibit, Munich, Germany - March 12-15, 2001.
I hope to update this list regularly to keep up with the new architectures being developed. Any feedback is appreciated, be it on new developments, updates to listed entries or even corrections to erroneous fields. I hope to expand the list to include the software projects undertaken in the reconfigurable computing field, including co-compilation, PAR and task allocation/scheduling ones. Any recommendations and/or suggestions are always greatly appreciated.

As per Dr. Guccione's case, all email addresses have been modified for no-spamming purposes. Email addresses listed on this page contain the letters "ns". To contact someone using their email address, edit out those two letters.

Rami Abielmona - rabielmo@site.uottawa.ca.ns - 2005
  • CALISTO
  • CHESS Array
  • Colt
  • CS2000 Family
  • D-Fabrix
  • DP-FPGA
  • DReAM Array
  • FIPSOC
  • GARP
  • Kress Array
  • MATRIX
  • MECA Family
  • MOLEN
  • MorphoSys
  • PADDI-1
  • PADDI-2
  • Pleiades
  • PipeRench
  • RaPiD
  • RAW
  • REMARC
  • XD1

    • CALISTO
    Name origin Configurable ALgorithm-adaptive Instruction Set TOpology
    Year of first publication 2000
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity TBD
    Mapping TBD
    Structure Mesh-based
    Application examples TBD
    Contact information TBD
    Web page http://www.broadcom.com/siliconspice.html
    Email address TBD
    Source(s)
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Single-chip communication processor aimed at applications such as echo cancellation and packetization
  • Replaces up to 10 traditional DSP discrete components
  • Featured with an IDE that includes an Optimizing C Compiler and Multiprocessor Debug Environment

    • CHESS Array
    Name origin Floorplan is chessboard-like
    Year of first publication 1999
    Logical architecture Interleaved ALUs and switchboxes
    Interconnect architecture 16 buses in each row and column
    Granularity 4-bit, multi-granular
    Mapping JHDL compilation
    Structure Mesh-based
    Application examples Multimedia
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • A. Marshall et al.: A Reconfigurable Arithmetic Array for Multimedia Applications; Proc. ACM/SIGDA FPGA99, Monterey, Feb. 21-23, 1999
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Chess-like interleaving of ALUs and switchboxes
  • Supports embedded RAM, and cycle-by-cycle reconfiguration through ALU communication

    • Colt
    Name origin TBD
    Year of first publication 1996
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 1 and 16 inhomogeneous
    Mapping Run-time reconfiguration
    Structure Mesh-based
    Application examples Highly-dynamic reconfigurable
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • R. A. Bittner et al.: Colt: An Experiment in Wormhole Run-time Reconfiguration; SPIE Photonics East '96, Boston MA, USA, Nov. 1996
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Data stream contains both routing and functionality configuration data to all processing elements (PEs)
  • Each interconnected functional unit (IFU) contains an ALU, a barrel shifter and a decision unit

    • CS2000 Family
    Name origin TBD
    Year of first publication TBD
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity TBD
    Mapping TBD
    Structure Mesh-based
    Application examples TBD
    Contact information TBD
    Web page http://www.chameleonsystem.com
    Email address TBD
    Source(s)
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Reconfigurable logic coupled with a RISC processor and a PCI controller
  • Reconfigurable fabric can be modified within a single clock cycle

    • D-Fabrix
    Name origin D stands for "Data" and "Dynamic", stressing the regularity of the "computing fabric"
    Year of first publication 1999
    Logical architecture Interleaved ALUs and switchboxes
    Interconnect architecture 16-bit busses in each row and column
    Granularity 4-bit, multi-granular
    Mapping Verilog, VHDL, Handel-C and Matlab
    Structure Mesh-based
    Application examples Multimedia, Wireless LAN and low-power mobile
    Contact information Elixent Ltd., Castlemead, Lower Castle Street, Bristol, BS1 3AG, UK
    Phone number: +44 117 917 5770
    Fax number: +44 117 917 5779
    Web page http://www.elixent.com
    Email address info@elixent.com.ns
    Source(s)
  • A. Marshall et al.: A Reconfigurable Arithmetic Array for Multimedia Applications; Proc. ACM/SIGDA FP GA99, Monterey, Feb. 21-23, 1999
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Chess-like interleaving of ALUs and switchboxes
  • Supports embedded RAM, and cycle-by-cycle reconfiguration through ALU communication
  • Adopted by Toshiba as a reconfigurable accelerator for the MeP RISC processor
  • Founded in October 2000 and based on the CHESS architecture, the first product is the DFA-1000

    • DP-FPGA
    Name origin Datapath FPGA
    Year of first publication 1994
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 1 and 4-bit, multi-granular
    Mapping Switchbox routing
    Structure Mesh-based
    Application examples Regular datapaths
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • D. Cherepacha and D. Lewis: A Datapath Oriented Architecture for FPGAs; Proc. FPGA94, Monterey, CA, USA, February, 1994
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Datapath blocks consist of 4-bit slices, with each slice consisting of a LUT, a carry chain and a 4-bit register
  • Separate data and control routing resources

    • DReAM
    Name origin Dynamically Reconfigurable Architecture for Mobile Systems
    Year of first publication 2000
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 8 and 16-bit
    Mapping Nearest-neighbour and segmented buses
    Structure Mesh-based
    Application examples Next generation wireless
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • J. Becker et al.: Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication System; Proc. FCCM00, Napa, CA, USA, April 17-19, 2000
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Reconfigurable units contain processing units, barrel shifters, controllers and DPRAM
  • Designed for next-generation wireless applications

    • FIPSOC
    Name origin FIeld-Programmable System-On-Chip
    Year of first publication 2000
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 4-bit multi-granular
    Mapping Undisclosed
    Structure Mesh-based
    Application examples Telecommunication and data communication
    Contact information TBD
    Web page http://www.sidsa.com
    Email address TBD
    Source(s)
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Contains a 8051 microcontroller, a reconfigurable architecture and a reconfigurable analog array
  • Digital macro cells (DMCs) each contain a lookup table (LUT), latches, a counter, a shift register, an adder and RAM
  • Configurable analog blocks (CABs) each contain differential amplifiers, comparators, converters and so on

    • GARP
    Name origin TBD
    Year of first publication 1997
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 2-bit
    Mapping Heuristic routing
    Structure Mesh-based
    Application examples Loop acceleration
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • J. Hauser and J. Wawrzynek: Garp: A MIPS Processor with a Reconfigurable Coprocessor; Proc. IEEE FCCM97, Napa, April 16-18, 1997
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Basic functional unit contains reconfigurable ALUs
  • Host and reconfigurable logic share same memory hierarchy

    • Kress Array
    Name origin First implementation by Rainer Kress (see Ph.D. thesis, University of Kaiserslautern)
    Year of first publication 1995
    Logical architecture Coarse grain rDPUs (reconfigurable datapath units)
    Interconnect architecture Nearest neighbour ports (number and width selectable), along with a back bus segment architecture
    Granularity KressArray Family select pathwidth
    Mapping (Co)-compilation and KressArray design space explorer
    Structure Mesh-based wiring-by-abutment-Matrix of uniform or mixed rDPUs
    Application examples Adaptable
    Contact information Reiner Hartenstein
    Web page http://kressarray.de
    Email address hartenst@rhrk.uni-kl.de.ns
    Source(s)
  • Ph. D. theses by Rainer Kress, Ulrich Nageldinger, Michael Herz (Univ. of Kaiserslautern)
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Datapath blocks are reconfigurable units, or rDPUs, serving as routers, operators or both
  • Can support any C language operator

    • MATRIX
    Name origin Multiple Alu archiTecture with Reconfigurable Interconnect eXperiment
    Year of first publication 1996
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 8-bit multi-granular
    Mapping Multi-length
    Structure Mesh-based
    Application examples General purpose
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • E. Mirsky, A. DeHon: MATRIx: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources; Proc. IEEE FCCM96, Napa, CA, USA, April 17-19, 1996
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Basic functional units (BFUs) include ALU, multiplier, instruction and data memory and a controller

    • MECA Family
    Name origin TBD
    Year of first publication 2000
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity Multi-granular
    Mapping Undisclosed
    Structure Mesh-based
    Application examples Telecommunication and data communication
    Contact information TBD
    Web page http://www.malleable.com
    Email address TBD
    Source(s)
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Intended as a family of DSPs
  • Optimized for voice over IP

    • MOLEN
    Name origin Moulin: the bit crunching mill
    Year of first publication 2001
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity TBD
    Mapping TBD
    Structure TBD
    Application examples Multimedia IP cores (MPEG-2 encoder/decoder, SAD, DCT, IDCT)
    Contact information Dr. S. Vassiliadis, Delft University of Technology
    Julianalaan 134
    2628 BL Delft
    The Netherlands
    Web page http://ce.et.tudelft.nl/MOLEN
    Email address S.Vassiliadis@ewi.tudelft.nl.ns
    Source(s)
  • S. Vassilisadis, et al.: The Molen Polymorphic Processor; IEEE Transactions on Computers, pp. 1363-1375, November 2004, Volume 53, Issue 11
  • S. Vassilisadis, et al.: The Molen pu-coded Processor; Proc. of 11th International Conference on Field-Programmable Logic and Applications (FPL), Springer-Verlag Lecture Notes in Computer Science (LNCS) Vol. 2147, pp. 275-285, Belfast, UK, August 2001
    • Comments
  • TBD
  • Provide a Delft Workbench semi-automatic tool for reconfigurable computing software support, including hardware/software partitioning, task scheduling and run-time integration and validation of reconfigurable modules

    • MorphoSys
    Name origin Morphoing System
    Year of first publication 1999
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 16-bit
    Mapping Manual placement and routing
    Structure Mesh-based
    Application examples Undisclosed
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • H. Singh, et al.: MorphoSys: An Integrated Re-configurable Architecture; Proc. of the NATO RTO Symposium on System Concepts and Integration, Monterey, CA, USA, April 20-22, 1998
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • MIPS-like processor with extended instruction set
  • Reconfigurable logic features ALU, multiplier, shifter, register file and context registers

    • PADDI-1
    Name origin Programmable Arithmetic Device for DSP
    Year of first publication 1990
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 16-bit
    Mapping Routing
    Structure Crossbar-based
    Application examples DSP
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • D. Chen and J. Rabaey: PADDI: Programmable arithmetic devices for digital signal processing; VLSI Signal Processing IV, IEEE Press 1990
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Consists of arithmetic execution units (EXUs) connected to a central crossbar switchbox

    • PADDI-2
    Name origin Programmable Arithmetic Device for DSP
    Year of first publication 1993
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 16-bit
    Mapping Routing
    Structure Crossbar-based
    Application examples DSP and others
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • A. K. W. Yeung, J.M. Rabaey: A Reconfigurable Data-driven Multiprocessor Architecture for Rapid Prototyping of High Throughput DSP Algorithms; Proc. HICSS-26, Kauai, Hawaii, Jan. 1993
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Consists of arithmetic execution units (EXUs) connected to a central crossbar switchbox

    • Pleiades
    Name origin TBD
    Year of first publication 1997
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity Multi-granular
    Mapping Switchbox routing
    Structure Crossbar-based
    Application examples Multimedia
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • J. Rabaey: Reconfigurable Computing: The Solution to Low Power Programmable DSP; Proc. ICASSP97 Munich, Germany, April 1997
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Consists of arithmetic execution units (EXUs) connected to a central crossbar switchbox

    • PipeRench
    Name origin TBD
    Year of first publication 1998
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 128-bit
    Mapping Scheduling
    Structure Linear array-based
    Application examples Pipelining
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • S. C. Goldstein et al.: PipeRench: A Coprocessor for Streaming Multimedia Acceleration; Proc. ISCA99, Atlanta, May 2-4, 1999
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Contains a state memory, an address translation table, data controllers, a bus controller and a configuration controller
  • While a stage is being executed, the reconfigurable architecture can be changed with another pipelined stage

    • RaPiD
    Name origin Reconfigurable Pipelined Datapath
    Year of first publication 1996
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 16-bit
    Mapping Channel routing
    Structure Linear array-based
    Application examples Pipelining
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • C. Ebeling et al.: RaPiD: Reconfigurable Pipelined Datapath
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Each functional unit contains an integer multiplier, integer ALUs, datapath registers and RAM
  • While a stage is being executed, the reconfigurable architecture can be changed with another pipelined stage

    • RAW
    Name origin Reconfigurable Architecture Workstation
    Year of first publication 1997
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 8-bit multi-granular
    Mapping Switchbox routing
    Structure Mesh-based
    Application examples Experimental
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • E. Waingold et al.: Baring it all to Software: RAW Machines; IEEE Computer, September 1997, pp. 86-93
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Offers a six-stage pipeline
  • Provides both static and dynamic network and routing


  • REMARC
    Name origin REconfigurable Multimedia ARray Coprocessor
    Year of first publication 1998
    Logical architecture TBD
    Interconnect architecture TBD
    Granularity 16-bit
    Mapping Unavailabe information
    Structure Mesh-based
    Application examples Multimedia
    Contact information TBD
    Web page TBD
    Email address TBD
    Source(s)
  • T. Miyamori and K. Olukotun: REMARC: Reconfigurable Multimedia Array Coprocessor; Proc. ACM/SIGDA FPGA98, Monterey, Feb. 1998
  • Reiner Hartenstein's embedded tutorial
    • Comments
  • Tightly coupled to a MIPS-II processor
  • Nanoprocessors are provided with memory attached to a global control unit

    • XD1
    Name origin Consisten with other product names (Cray X1, Cray XT3 MPP)
    Year of first publication 2004
    Logical architecture High performance Linux operating system running on AMD Opteron 64-bit processors, along with six application acceleration processors based on Xilinx Virtex II Pro (Virtex 4 later this year) FPGAs
    Interconnect architecture RapidArray interconnect directly connects processors over high-speed, low-latency pathways
    Granularity 1-bit multi-granular
    Mapping Verilog, VHDL, Handel-C, Matlab/Simulink, Impulse-C and Mitrion compilation
    Structure Mesh-based
    Application examples Searching, sorting, signal processing and reconfigurable computing
    Contact information Dave Strenski or Luc Ostiguy
    Web page http://www.cray.com/products/xd1/index.html
    Email address stren@cray.com.ns or luco@cray.com.ns
    Source(s)
  • D.H. Brown's White Paper: Cray XD1 Brings High-Bandwidth Supercomputing to the Mid-Market
  • Cray XD1 Datasheet
    • Comments
  • System consists of chassises that can be wired together to make very large cluster-like systems with a fast interconnect
  • Each chassis can have 12 or 24 Opteron processor cores and 6 Xilinx Virtex II Pro chips

    • Interesting Quote

    "Simply stated, it is sagacious to eschew obfuscation."
    --Norman Augustine
    Rami S. Abielmona

    School of Information Technology and Engineering (SITE), University of Ottawa
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    Email: rabielmo@site.uottawa.ca.ns
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