SYSC5603 (ELG6163) Digital Signal Processing Microprocessors, Software and Applications

References

Books

[Ackenhusen99] J. G. Ackenhusen, Real-time Signal Processing: Design and Implementation of Signal Processing Systems, Prentice Hall, 1999.

[Constantinides04] G. A. Constantinides, P. Y. K. Cheung, W. Luk, Synthesis and Optimization of DSP Algorithms, Academic Publishers, 2004.

[Chassaing05] R. Chassaing, Digital Signal Processing and Applications with the C6713 and C6416 DSK, John Wiley & Sons, 2005.

[Kester03] W. Kester, Mixed-Signal and DSP Design Techniques, Analog Devices, Newnes, 2003.

[Kuo05] S. M. Kuo, W. S. Gan, Digital Signal Processors: Architectures, Implementations, and Applications, Prentice Hall, 2005.

[Lapsley97] P. Lapsley, J. Bier, A. Shoham, E. A. Lee, DSP Processor Fundamentals: Architecture and Features, IEEE Press, 1997.

[Meerbergen] J. van Meerbergen, Embedded Multimedia Systems in Silicon, http://www.ics.ele.tue.nl/~jef/education/5p520/, Technology Eindhoven, Department ICS, Division ES.

[Meyer04] U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Array, Springer-Verlag, New York, 2004.

[Mitra06] S. K. Mitra, Digital Signal Processing, A Computer-Based approach, McGraw Hill, 2006.

[Oppenheim98] A. V. Oppenheim, R. W. Schafer, Discrete-time signal processing, 2nd edition, Prentice Hall, 1998.

[Parhi 99] K. K. Parhi, VLSI Signal Processing Systems, Design and Implementation. John Wiley & Sons, Inc., New York, 1999. Slides

[Shenoi06] B. A. Shenoi, Introduction to Digital Signal Processing and Filter Design, John Wiley & Sons, Inc., 2006.

[Smith97] S. Smith, The Scientist and Engineer's Guide to Digital Signal Processing, California Technical Publishing, 1997.

[Sriram00] S. Sriram, S. S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization, Marcel Dekker Inc., 2000.

[Wanhammar99] Lars Wanhammer, DSP Integrated Circuits, Academic Press, San Diego, 1999.

Journal papers

[Adams04] L. Adams, “Semiconductor options for real-time signal processing,” EDN, November 25, 2004, p. 87-94.

[Allen05] R. Allen, “Compiling high-level languages to DSPs: automating the implementation path,” IEEE Signal Processing Magazine, Vol. 22, no 3, pp. 47-56, 2005.

[Bondalapati00] K. Bondalapati, V. K. Prasanna, Reconfigurable Computing: Architectures, Models and Algorithms (PDF),Current Science: Special Section on Computational Science 78(7), April 2000.

[Cravotta05] R. Cravotta,” EDN 2005 DSP Directory: Targeted DSPs take aim,” EDN, 2005.

[Duhamel90] P. Duhamel, M. Vetterli, “Fast Fourier Transform: A tutorial review and a state of the art”, Signal Processing 19, pp. 259-299, 1990

[Eyre00] J. Eyre, and J. Bier, "The evolution of DSP processors," IEEE Signal Processing magazine, March 2000, vol. 17, no.2, pp. 43-51.

[Fridman00] J. Fridman, "Sub-word parallelism in digital signal processing -- applying the TigerSHARC architecture," IEEE Signal Processing Magazine, vol. 17, no. 2, pp. 27-35, March 2000.

[Guerra96] L. M. Guerra, Behavioral Level Guidance Using Property-Based Design Characterization, Ph.D. thesis, Berkeley, 1996.

[Hu92] Y. H. Hu, “CORDIC-based VLSI architecture for digital signal processing,” IEEE Signal Processing Magazine, July 1992, pp. 16-35.

[Jerraya04] A.A. Jerraya, W. Wolf,” The What, Why, and How of MpSOCs,” from Multiprocessor Systems-on-Chips, Morgan Kaufman, 2004

[Kumar05] R. Kumar, D. M. Tullsen, N.P. Jouppi, P. Ranganathan, “Heterogeneous Chip Multiprocessors,” IEEE Computer, Volume: 38, Issue: 11, pp. 32-38, 2005.

[Li03] W Li, Studies on implementation of low power FFT processors, Thesis, Linköpings University, 2003

[Liu71] B. Liu, “Effect of Finite Word Length on the Accuracy of Digital Filters - A Review,” IEEE Trans. on Circuit Theory, Vol. 18, No 6, Nov. 1971

[McFarland88] Michael C. McFarland, Alice C. Parker, Raul Camposano, "Tutorial on high-level synthesis", Proceedings of the 25th ACM/IEEE conference on Design automation, pp. 330-336, June 1988.

[Moretti05] G. Moretti,” Design complexity requires system-level design,” EDN, 2005.

[Parker96] D.A. Parker, K.K. Parhi , “Area-efficient parallel FIR digital filter implementations,” Proceedings of International Conference on Application Specific Systems, Architectures and Processors, 1996. ASAP 96.

[Parhi89] K.K. Parhi, “Algorithm transformation techniques for concurrent processors,” Proc. IEEE, vol. 77(12), pp. 1879–1895, December 1989.

[Parhi89_2] K.K. Parhi and D.G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters,” IEEE Trans. Acoustics, Speech, Signal Processing, vol. 37(7), pp. 1099–1135, July 1989.

[Parhi92] K. K. Parhi, C.-Y. Wang, and A. P. Brown, “Synthesis of control circuits in folded pipelined DSP architectures,” IEEE J. Solid-State Circuits, vol. 27, pp. 29-43, Jan. 1992.

[Parhi95] K. K. Parhi, High-level algorithm and architecture transformations for DSP synthesis, The Journal of VLSI Signal Processing, Vol 9, pp 121-143, 1995

[Richards04] M. A. Richards, and G. A. Shaw, "Chips, Architectures and Algorithms: Reflections on the Exponential Growth of Digital Signal Processing Capabilities," Submitted to IEEE Signal Processing Magazine, 2004

[Rabay98] J. M. Rabay et al (Ed.), “VLSI Implementation Fuels the Signal Processing Revolution,” IEEE Signal Processing Magazine, Jan. 1998.

[Seshan98] N. Seshan, “High VelociTI Processing,” IEEE Signal Processing Mag, March 1998, pp. 86-101 (Tutorial on TMS320C6000 VelociTI Advanced VLIW Architecture)

[Sung95] W. Sung, K. Kum, “Simulation Based Word Length Optimization Method for Fixed-Point Digital Signal Processing Systems,” IEEE Trans. Signal Processing, vol. 43, pp. 3087 -- 3090, Dec. 1995.

[Thiele05] L. Thiele, E. Wandeler; S. Chakraborty, “Performance analysis of multiprocessor DSPs: a stream-oriented component model,” IEEE Signal Processing Magazine, Vol. 22, no 3, pp. 38-46, 2005.