ELG6158 (SYSC 5508) DIGITAL SYSTEMS ARCHITECTURE

PROFESSOR

Miodrag Bolic

School of Information Technology and Engineering (SITE), University of Ottawa
Tel: (613) 562-5800 x 6224, Fax: (613) 562-5175
Email: mbolic@site.uottawa.ca

Web: www.site.uottawa.ca/~mbolic

Office Hours: Friday, 12:45-14:00, CBY A-616

COURSE DESCRIPTION

New architectural concepts are introduced. Discussion of programmable architectures (micro-controllers, DSPs, GP) and FPGAs. Memory interfacing. Scalable, superscalar, RISC, CISC, and VLIW concepts. Parallel structures: SIMD, MISD, and MIMD. Fault tolerant systems and DSP architectures. Examples of current systems are used for discussions.

COURSE SCHEDULE

Activity	Time	Location
LEC	Monday, 11:30 -13:00	CBY 015
LEC	Friday, 11:30 -13:00	CBY 015

SUGGESTED TEXTS

There is no textbook

Single cycle and pipelined RISC processors

[1] David A. Patterson, John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann; 3^rd edition, August 2, 2004, ISBN: 1558606041.

Advanced computer architectures

[2] John L. Hennessy, David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann; 4rd edition, 2006.

[3] William Stallings, Computer Organization and Architecture, Prentice Hall; 6^th edition, July 15, 2002, ISBN: 0130351199.

Embedded multiprocessors

[4] Wayne Wolf, High-Performance Embedded Computing: Architectures, Applications and Methodologies, Morgan Kaufman, 2007

PREREQUISITES

Knowledge of digital design

TOPICS DISCUSSED

(This is a very preliminary schedule)

Lecture #	Week of	Topic	Literature	Study topics
	Jan, 4	Introduction,
	Jan 11	FPGAs, Single cycle processors	[1]	Design of register files, Alfredo Shadow register files, Josip
	Jan 18	Pipelining	[1]
	Jan 25	Pipelining, Branch prediction	Slides: http://home.eng.iastate.edu/~zzhang/courses/cpre585-f04/slides/lecture9.ppt Papers: Tse-Yu Yeh and Yale N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," ISCA 1992.
	Feb 01	Caches, Virtual memory	[1]
	Feb 08	Virtual memory
	Feb 22	Virtual memory – putting it all together Advanced topics in VM and cache design	Virtual Memory II, Virtual Memory III Dynamic Memory Allocation I
	Mar 01	Profiling Handling exceptions	Guest lecturer: Dr. Subhasis Banerjee Exceptions
	Mar 08	MMX and SSE extensions Configurable processors
	Mar 15	Configurable processors - Tensilica Microcontroller architecture Vector processors,	Guest lecturer: Vishal Thareja
	Mar 19	DSP processors, DSP Processor Evolution Intro to superscalar and VLIW VLIW	VLIW Architecture and programming of TMS320C6x Lecture slides from: 31611 Real Time Signal Processing · Chapter 2 pages 1-60 · Chapter 7 Chapter 12 pages 1-32Slides
	Mar 26	Superscalar processors,
	April	Project presentation

MARKING SCHEME

· Final exam (40%)

· Presentation and report (24%)

· Design Projects (36%)

PAPER ANALYSIS AND PRESENTATION

Every student will need to do 2 analyses of existing solutions and to write his/her analysis in form of the research paper.

What to analyze

Research papers should include survey papers (IEEE or ACM journals) or general research papers. Please do not copy sentences from the papers: see the paper on plagiarism: How to Handle Plagiarism: New Guidelines .

Style

The goal is to present several industrial and/or academic solutions, understand and present performance metrics and then give qualitative or quantitive comparison of those solutions. Please see this link as an example:

Daniel Shapiro, “Design Automation for an ASIP Empowered Asymmetric MPSoC,” report, University of Ottawa, 2009.

Here, existing solutions are analyzed. Some design criteria are selected and comparison is presented in the table.

Grading

· Formatting, Style and English (References have to be in proper form) 30%. Please take a look at the proposed format: IEEE format

· Relevance of the selected papers: 10%

· Quality of the analysis: 30%

· Quality of comparison: 30%

Due dates and turn-in instructions

The analysis should be at least 3 pages long. You have to follow formatting from IEEE format, which means that you need to use the same font, no line spacing and defined margins. The studies have to be submitted 3 weeks after the lecture.

Tips for a good assignment completion

Here's a list of things to keep in mind when preparing this assignment to get as much credit as possible:

• Organization matters. Your report should have a sort of introduction, appropriate sections, and a summary
• References. You should also list all references you used to write. Those are not limited to actual lecture notes, book chapters, articles, etc
• Definitions and proofs. If something was derived in class on the board, it needs to be included in your report. If some function was used in derivations that wasn't explicitly explained on the slides or in lecture, it is your job to find how this function is defined.
• If a schematic is explained in the class, your job is to explain every part of this schematic.
• Examples and illustrations. It's much easier for the readers to understand something if they see it used in context that they can relate to. And sometimes a  single picture can explain a lot more than a page of words.

Proofread, proofread.

Topics

1. Design of the register file

· Implementation of the register file for RISC processors

· Microarchitecture of the register file

· Different design approaches

· Implementation of the floating-point register file

· Comparison of different approaches based on area requirements, number of ports, …

· Do not consider register file for advanced architectures such as superscalar and VLIW

2. Shadow and split register files

· Analysis of implementation of shadow register files

· Implementation of shadow register files for configurable processors

· Comparison of different implementations

· Implementation of split register file (for example in Texas Instruments C6x DSP processors)

· Comparison of different implementations

3. New trends in FPGA design – configurable processor design

· Design of configurable processors on FPGA platforms

· Comparison of architectures and software solutions

4. New trends in FPGA design – multiprocessors

· Hardware and software tools for multiprocessors design on FPGA

· Comparison of different architectures

· Application of multiprocessing systems on FPGAs

5. Cache controller design

· Internal datapath of a cache controller

· Example of cache controller implementations (for example ARM L210 Cache Controller)

· Performance metrics in designing cache controllers

· Comparison of cache controller designs

6. Profiling techniques (solutions for simple RISC processors)

· Trace based analysis

· Sampling

· Instrumentation based techniques

· Analysis of profiling solutions for embedded systems

7. Support for exceptions

8. Branch predication

· Definition

· Examples of implementation

· Software pilelining

9. Branch prediction techniques for real time systems

· Examining worst case execution

· Analyzing branch predictors for real-time execution

10. Implementation of the memory management unit

· Detailed implementation of the MMU

· Case study

11. Memory system implementation on Intel Core i7

12. Architecture of the Cell processor

13. Description of the architecture of Lion 3 processor

14. VM memory operations during dynamic memory operation

· Analyze behavior of VM during malloc operation

· Implementing a simple allocator

15. Linking

· Relocation

· Dynamic linking with shared libraries

· Position-independent code

· Tools for manipulating object files

PROJECT

Project should be related to the course material. It can include architecture for signal processing, configurable processors, parallel processors, ... So, you propose the project.

Deadlines

• Project proposals are expected by February 8^th and they will be approved/not approved during the week of February 8th.

• The first phase of the project should be finished by March 8^th and project report for the first phase should be submitted by then.

• Project have to be demonstrated and report submitted on April 5rd

• Grade: 15% Project Proposal, 20% first phase report, 40% Demonstration, 25% final report

Project report

Proposal: The purposes of writing a project proposals are: (i) to determine the topic, (ii) to show that preliminary study of the subject materials have been done, (iii) to assess the likelihood of success of the project, (iv) to give the plan to carry out the project. You should submit a two to three pages proposal to the instructor for approval of the project. In the case of the rejection of the proposal, the team must come up with an revised proposal or an alternate new proposal before a deadline specified in the course outline. Preliminary discussion with the instructor can also be held in advance during their office hours. However, the opinion expressed by the teaching staff during these preliminary discussions are only suggestions. The team members are responsible to use their best judgement to prepare the proposal for approval.

The format of the proposal is as follows:

• title of the project

• project highlight -- explain what you want to do in this project,

• Motivation -- explain the significance of the proposed project and the relevance of the project to this course

• Prior art -- listing at least three previous works (papers, books, etc.) that reported work most closely related to the current project. Briefly review their approaches, advantages and shortcomings.

• Define the architecture that you will implement, describe software approaches

• Define how you will test and what will be the final results for the demonstration

Report: A type-written, hardcopy project report, as well as an electronic version (including source code, design files developed) are to be submitted at the end of the semester and at the end of the first phase. The length of the report is not restricted. However, the report must be include the following sections:

• Introduction: Motivation and backgrounds.

• Main body of report. Depending on types of project, this part may include method used, approaches taken, problem description, etc.

• Conclusion and discussion: Highlight your achievement in this project and things may be done in the future.

Potential projects:

Simulation of a configurable processor using Coware tools – 3 Labs will be provided.

Design of a configurable processor using Tensilica tools – 5 licences are available

Multiprocessor design using NIOS II processors

Example project: Multiprocessor design using NIOS II processors

· Design a system for performing Kalman filtering operation on a NIOS II processor and profile its execution

· Design a multiprocessor system with 2, 4 and 8 processors

· Partition the code to be implemented on multiple processors

· Determine the speedup of the execution

Example project: Designing custom instructions for XTensa

· Implement Kalman filtering algorithm in software and run it on Xtensa processor.

· Configure high level parameters of the XTensa processor to achieve speedup

· Implement hardware accelerators in TIE to achieve further speedup.

Example project: Proposing a processor for statistical signal processing

· Analyze a number of statistical signal processing algorithms (using Matlab or some C libraries)

· Perform analysis of the frequency and complexity of used instructions

· Propose a processor that would speed up execution of common statistical signal processing programs

· Propose design of that processor using Tensilica tools.